We are designing compute architectures that treat analog computation as a feature, not a limitation. The circuits you design here are not peripheral — they are the core compute fabric. You will work at the intersection of device physics, circuit design, and machine learning, helping define what the next generation of AI hardware looks like at the transistor level.

• Design and simulate analog circuits for in-memory compute — including precision current/voltage-domain inference structures, novel memory-compute cells, and supporting signal path elements
• Work directly with the architecture team to translate system-level requirements into circuit specifications and back again
• Characterise and mitigate the effects of process, voltage, temperature, and long-term drift (PVT-D) in novel materials and non-standard process nodes
• Contribute to our custom EDA tooling, including Verilog-A models, characterisation flows, and validation infrastructure
• Collaborate across the stack — your design decisions have direct consequences for compiler targets, model quantisation, and system-level energy budgets

• Strong foundation in analog circuit design — transistor-level understanding of noise, matching, bandwidth, and power trade-offs
• Hands-on experience with custom circuit design in standard CMOS processes; familiarity with non-standard or emerging process nodes is a plus
• Comfort with simulation environments (Spectre, HSPICE, or equivalent); prior experience building compact models or behavioural models in Verilog-A or similar is valued
• Experience with mixed-signal design or analog front-ends for sensing and signal processing
• Genuine curiosity about machine learning and how model architectures interact with hardware constraints — you don't need to be an ML researcher, but you should want to understand the connection
• Prior work at a deep-tech startup, research lab, or equivalent environment where ownership and ambiguity are the norm

• Background in neuromorphic circuits, compute-in-memory, or resistive memory (RRAM, memristors, PCM)
• Experience with layout, parasitic extraction, and silicon bring-up

Commercial EDA tools were not built for the architectures we are designing. We are building our own — and we want engineers who think designing tooling is as interesting as the hardware it serves. You will work on software that bridges the gap between novel circuit structures, model representations, and physical design constraints, using systems languages chosen for performance and correctness.

• Design and build EDA tooling infrastructure for analog and mixed-signal circuit design — including netlist parsers, design rule engines, characterisation automation, and verification flows
• Work in Zig, Rust, and/or C on performance-critical tool components; contribute to a codebase where correctness guarantees are a design goal, not an afterthought
• Build AI-assisted design tools: design-space exploration, automated schematic generation, constraint propagation, and layout assist
• Integrate with standard data formats (SPICE, Verilog-A, GDSII, LEF/DEF) and open-source EDA ecosystems
• Work closely with analog designers and compiler engineers to understand requirements and build tools that actually reflect how designers think

• Strong systems programming skills in at least one of: C, Zig, or Rust — comfort with low-level memory management, performance profiling, and building reliable tooling
• Experience building developer tools, compilers, or structured data pipelines; you understand how to design for both correctness and usability
• Familiarity with EDA concepts — even at a high level — is strongly valued; prior work with SPICE, OpenROAD, KLayout, Magic, or similar tools is a plus
• Exposure to ML-assisted design, constraint solving, or formal methods is a plus
• A mindset that treats tooling as a first-class technical problem, not scaffolding — the tools we build have direct impact on what hardware is possible

• Prior contributions to open-source EDA tools or hardware description languages
• Experience with language design, IR design, or domain-specific languages (DSLs)

Getting a 100B-parameter model to run on a fundamentally different compute architecture is not just a software problem — it requires rethinking how models are represented, partitioned, and lowered to hardware. You will build the compiler stack that bridges PyTorch and TensorFlow model graphs to our custom hardware ISA, working across the full pipeline from graph-level optimisation to low-level instruction scheduling.

• Design and implement compiler passes for graph-level optimisation: operator fusion, tiling, quantisation-aware lowering, and memory layout transformations
• Work on the backend: map model operations to our custom hardware ISA, handling resource allocation, scheduling, and memory management for a spatial, in-memory compute architecture
• Build and maintain compiler infrastructure using MLIR and/or LLVM; contribute to dialect design and lowering pipelines for novel compute primitives
• Develop model partitioning strategies (tensor, pipeline, and data parallelism) tuned to our hardware's specific topology and memory hierarchy
• Profile and benchmark end-to-end model execution; own the feedback loop between compiler decisions and measured hardware performance

• Experience building production compiler infrastructure — LLVM, MLIR, TVM, XLA, or equivalent; familiarity with dialect design, IR transformations, and lowering pipelines
• Strong algorithmic problem-solving: you can move from a high-level problem statement to a correct, efficient implementation
• Solid working knowledge of ML frameworks (PyTorch, TensorFlow, ONNX) and how models are represented and executed at the graph level
• Comfort with C++ and Python; experience with systems languages (Rust, Zig) is valued
• Prior work mapping models to novel or non-GPU hardware — ASICs, FPGAs, or custom accelerators — is a strong plus

• Contributions to open-source compiler projects (Torch-MLIR, ONNX-MLIR, Triton, TVM)
• Understanding of analog hardware constraints and how they affect numerical precision, quantisation strategies, and operator support